Simple VHDL Problem with synchronous/asynchronous logic -

i stuck now. following module working fine in simulation not work in hardware. simple, can't figure out why not working. essentially, module gets 2 input operands (op1, op2), 2 comand signals (fu_op, fu_imm) , clock. following 2 evaluations executed in consecutive clock cycles:

s0 (x) tx <= x; r <= simple xor, or, , input x  f0(tx, x, y) r <= simple xor, or, , input x, y , tx! 

i guess somehow passing of tx f0 not working. there wrong how try handle case of tx, might have forgotten in sensitivity list?

many input!

    entity test_module     port     (       op1    : in  std_logic_vector(31 downto 0);      -- first input operand       op2    : in  std_logic_vector(31 downto 0);      -- second input operand       fu_op  : fu_op_type;                             -- opcode       fu_imm : in std_logic_vector(7 downto 0);        -- immediate       clk    : in  std_logic;                          -- clock       res    : out std_logic_vector(31 downto 0)       -- result     );     end;      architecture rtl of test_module        type res_sel_type (pass, s0, f0);         constant z : std_logic_vector(31 downto 0) := (others => '0');                                signal res_sel  : res_sel_type;       signal load     : std_logic := '0';        signal tx       : std_logic_vector(31 downto 0) := (others => '0');         procedure s0_proc       (         signal : in  std_logic_vector(31 downto 0);         signal r : out std_logic_vector(31 downto 0)       )               variable res : std_logic_vector(31 downto 0);       begin          r := ( a(6 downto 0) & a(31 downto 7) ) xor ( a(17 downto 0) & a(31 downto 18) ) xor ( z(2 downto 0) & a(31 downto 3) );        end;        procedure f0_proc       (         signal : in  std_logic_vector(31 downto 0);         signal b : in  std_logic_vector(31 downto 0);         signal c : in  std_logic_vector(31 downto 0);         signal r : out std_logic_vector(31 downto 0)       )               variable res : std_logic_vector(31 downto 0);       begin          r <= ( , b ) or ( ( or b ) , c ) ;        end;      begin        -- decode opcode       dec_op: process (fu_op, fu_imm)          variable tmp  : res_sel_type;         variable ld   : std_logic;        begin          -- default value         tmp  := pass;         ld   := '0';          if (fu_op = fu_fpga)            case fu_imm             -- compute s0, store first operand               when fpga_s0 =>                 ld  := '1';                           tmp := s0;             -- compute f0               when fpga_f0 =>                 ld  := '0';                           tmp := f0;                                                     when others =>                 -- leave default values               end case;               res_sel  <= tmp;            load     <= ld;                end if;             end process;        -- selection of output       sel_out: process (res_sel, op1, op2)        begin          case res_sel             when s0 =>            s0_proc(op1, res);                 when f0 =>                 f0_proc(tx, op1, op2, res);               end case;        end process;         sync: process(clk)         begin                 if clk'event , clk = '1'               if load = '1'                    tx <= op1;               end if;                end if;       end process;        end rtl;